This invention is directed to a dynamic divider circuit for dividing a clock signal by n-1, where n is an odd integer, and in particular to a dynamic divider circuit having an even division ratio for dividing a single phase clock signal.
Heretofore, divider circuits admitting of an even division ratio have been primarily comprised of two-phase circuits. Such two-phase circuits receive a first input clock signal .phi. and a second clock pulse .phi. having the same period but inverted with respect to the clock signal .phi.. Nevertheless, because the oscillatory circuits for providing such clock signals produce a single phase signal, an inverter is disposed intermediate the oscillatory circuit and the divider circuit to produce the second phase clock signal. Although, such two-phase clock operation of the divider circuit at high frequencies is required to provide an accurate electronic wristwatch, same results in excessive current consumption, thereby shortening the life of the battery utilized to power the electronic wristwatch. Accordingly, a dynamic divider circuit having an even division ratio and admitting of single phase operation to reduce current consumption is desired.